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For decades, advances in integrated circuits (IC) have been driven by continuous scaling down of planar IC technologies. As IC scaling rapidly approaches to technical brick wall, 3D IC heterogeneous integration emerges as a viable solution for future integrated electronics. Future complex system-on-a-chip (SoC) requires high-performance active devices, and(More)
This paper reports the first 8kV+ ESD-protected SP10T transmit/receive (T/R) antenna switch for quad-band (0.85/0.9/1.8/1.9-GHz) GSM and multiple W-CDMA smartphones fabricated in an 180-nm SOI CMOS. A novel physics-based switch-ESD co-design methodology is applied to ensure full-chip optimization for a SP10T test chip and its ESD protection circuit(More)
This paper reports a comprehensive electrostatic discharge (ESD) protection circuit co-design and analysis approach for high-frequency and high-speed ICs. Implemented in a 28nm CMOS, the ESD co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, parasitic ESD parameter extraction and ESD circuit evaluation for up to(More)
This paper presents design of an ultra-high precision bandgap voltage reference circuit in a 180nm BCDMOS 1P6M process. A novel current trimming technique is introduced to achieve high accuracy and low temperature coefficient. This bandgap voltage reference circuit achieves a low 17.1ppm temperature coefficient in measurement and 0.15% 3σ inaccuracy in(More)
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