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This paper derived a method of modeling litho-constrained layout in design stage. The model applies directly on design layout and does not require mask-synthesis steps. Results show we can capture design-relevant litho "hot-spots" within a matter of an hour on a large full-chip data. This method proves that the hot-spot information is embedded in original(More)
Peak temperature, local hotspots, and thermal gradients became critical issues with higher localized current densities resulting from the combination of higher performance and further device miniaturization. 3D vertical integration utilizing VIA first/VIA early technologies exacerbated that problem by the interaction of inter-die heat sources and(More)
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