Zoltan Francisc Baruch

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– Field-Programmable Gate Arrays (FPGAs) are flexible circuits that can be (re)configured by the designer. The efficient use of these circuits requires complex CAD tools. One of the steps of the design process for FPGAs is represented by placement. In this paper we present a genetic algorithm for the FPGA placement problem, in particular for the Atmel FPGA(More)
This paper presents the basic concepts in industrial video acquisition boards evaluation. The testing procedure is focused on real accuracy test (SNR measurements) and was applied to evaluate two main chipsets used in modern applications: Philips SAA713x and Conexant (Bt8xx and CX2338x). Simple programs developed to evaluate the accuracy performance are(More)
High speed serial interfaces represent the new trend for device-to-device communication. These systems require clock recovery modules to avoid clock forwarding. In this paper we present a high-speed clock recovery method usable with low-cost FPGAs. Our proposed solution features increased speed and reduced size compared to existing designs. The method(More)
This paper presents the design and implementation of a benchmarking system for QoS (quality of service). The application generates traffic patterns, measures and computes the QoS parameters and stores and displays the results both in numerical and graphical form. The main advantages of this system are the traffic patterns complexity, the accuracy of the(More)
This paper presents an enhanced approach for improving the prediction efficiency of the processor idle state selection of the cpuidle subsystem in the Linux kernel. Two methods for improving the prediction rate of processor idle states are proposed. The first is based on reinforcement learning and the second is based on the recent history of idle states.(More)
This paper presents the design and implementation of an embedded system for real-time network flow identification. The system identifies data flows based on packet inspection. The main advantage of this system is that it reduces significantly the processing time required for the flow identification. For the hardware implementation, a Xilinx Virtex-II Pro(More)
In this paper we present a specific routing algorithm for the Atmel 6002 FPGA circuit. We define a specific cost function and a specific way of handling the connectivity list, sorting it by two main criteria: the number of stored links and the competition's cost. We implemented a routing algorithm which simultaneously treats the global and local routing.(More)