Zih-Heng Chen

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In this article, we present a FPGA-based reconfigurable system for the advanced encryption standard (AES) algorithm. This proposed design, called diversified AES (DAES), has the variations of four parameters: the field irreducible polynomial, the affine transformation in the SubBytes, the offsets in the ShiftRows, and the polynomial in the MixColumns. The(More)
Recently, normal bases have been an appealing technique for hardware implementation in many applications, especially when finite fields are very large, such as the public key cryptosystems. In this article, a new viewpoint is introduced for performing the multiplication in the normal basis representation over binary field where the field defining(More)
The multiplicative inversion in finite field is much more complex than all field arithmetic operations. In this paper, a design of a simpler inversion module with lower complexity in GF(2<sup>m</sup>) using standard basis is proposed. It has the major improvement comparing with the design proposed by Wang et al. and Dinh et al. The implementations of those(More)
In the Rijndael, one can replace some variations to produce different ciphers, including the irreducible polynomial, the affine transformation in the SubByte, the offsets in the ShiftRow, and the polynomial in the MixColumn, to increase the variety of the Advanced Encryption Standard (AES) algorithm. In this article we present three types of MixColumn(More)
In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the(More)
Digital signal processing typically requires large number of mathematical operations to be performed repeatedly on the samples of data with less delay and power consumption. Multiplication is the fundamental arithmetic operation and determines the overall execution time of the processor. In this paper two high speed 32-bit Vedic multipliers are designed(More)
The Massey-Omura multiplier is a well-known sequential multiplier over finite fields GF(2<sup>m</sup>), which can perform multiplication in m clock cycles for the normal basis. In this article, the authors propose a new architecture to carry out the sequential multiplier using normal basis. The time complexity in each cycle of this new multiplier is O(1)(More)
Finite field is mainly used in communications. In those arithmetic operations, modular exponentiation is an important unit for most public-key cryptosystems and some error- correcting codes. In this paper, we propose an algorithm to compute multi-exponentiation on the normal basis. This algorithm, a multiplexer-based design, expands from Chiou and Lee's(More)
The mathematics of finite field has been widely applied on the design of core modules for cryptography systems. This paper presents one of the module designs of a VLSI computer aided design (CAD) system to bridge the gap between the finite field and the hardware for coding theory. It aims on the design automation of base-conversion between standard and(More)
This paper presents a research to strengthen the using of embedded system memory, including: Flash memory, SRAM, DRAM etc. For increasing the reliability on data storage, we use the conventional fault-tolerant mechanisms-Mirror and CRC techniques to carry out the forward protection at first. Furthermore we use the encryption and Reed-Solomon code to improve(More)