Zhiyin Zhou

Learn More
—A 6.0-13.5 GHz Alias-Locked Loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fV CO in the feedback path. In this implementation, a new architecture of high(More)
  • 1