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This paper proposes large-scale transient stability simulation based on the massively parallel architecture of multiple graphics processing units (GPUs). A robust and efficient instantaneous relaxation (IR)-based parallel processing technique which features implicit integration, full Newton iteration, and sparse LU-based linear solver is used to run the(More)
A 6.0-13.5 GHz Alias-Locked Loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fV CO in the feedback path. In this implementation, a new architecture of high frequency(More)
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