Zhixian Chen

Learn More
—We present a vertical-silicon-nanowire-based p-type tunneling field-effect transistor (TFET) using CMOS-compatible process flow. Following our recently reported n-TFET [11], a low-temperature dopant segregation technique was employed on the source side to achieve steep dopant gradient, leading to excellent tunneling performance. The fabricated p-TFET(More)
In this letter, HfO 2 based RRAM with varying device sizes are discussed with an analysis on their electrical characteristics. Device sizes of 60nm and 120nm were achieved by using different thickness of nitride spacer after 200nm contact hole is formed. Platinum (Pt) bottom electrode and Titanium Nitride (TiN) top electrode were used with HfO 2 dielectric(More)
—This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the(More)
—For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low(More)
Vertical Si nanowire (SiNW) gate-all-around MOSFETs with Ni-silicided nanowire tip is presented. The fabrication process is top-down CMOS compatible and is similar to previously reported vertical SiNW tunneling FETs (TFETs) where silicidation at the nanowire tip is done to segregate dopants at the channel interface for an abrupt junction. Also, for the(More)
We present a CMOS compatible p-type gate-all-around (GAA) vertical silicon nanowire tunneling field effect transistor (TFET) featuring Si 0.8 Ge 0.2 source with silicon channel. Besides heterojunction on source side, the highly abrupt doping profile at source-to-channel junction is achieved by low temperature dopant segregation. The fabricated devices(More)
  • 1