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The rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale someday. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. A cluster-on-chip architecture, as exemplified(More)
Low power is the first-class design requirement for HPC systems. Dynamic voltage and frequency scaling (DVFS) has become the commonly used and efficient technology to achieve a trade-off between power consumption and system performance. However, most the prior work using DVFS did not take into account the latency of voltage/frequency scaling, which is a(More)
Malware is a tremendous threat on the Internet. Current malware analysis systems focus on listing the malware behaviors, but make no mention of malware network behaviors which results in malware's self-duplication and self-propagation on the Internet. In this paper, we present a new method to extract malware network behaviors. Our method is based on dynamic(More)
Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and(More)
In the field of information security, risk assessment is the core of the risk management and control. This paper proposes a security risk assessment method based on threat analysis combined with AHP and entropy weight. This method has features that are suitable for website such as practical, easy operative and independent. And the AHP and entropy weight(More)
The concerns of data-intensiveness and energy awareness are actively reshaping the design of high-performance computing (HPC) systems nowadays. The Graph500 is a widely adopted benchmark for evaluating the performance of computing systems for data-intensive workloads. In this paper, we introduce a data-parallel implementation of Graph500 on the Intel(More)
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