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A wideband noise-cancelling low-noise amplifier (LNA) without the use of inductors is designed for low-voltage and low-power applications. Based on the common-gate-common-source (CG-CS) topology, a new approach employing local negative feedback is introduced between the parallel CG and CS stages. The moderate gain at the source of the cascode transistor in(More)
The influence of gate direct tunneling current on ultrathin gate oxide MOS ( nm nm, – nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low static-logic circuits. However, dynamic logic and analog(More)
Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the(More)
A 60-GHz injection-locked frequency divider (ILFD) with quadrature outputs is designed in 90-nm CMOS technology. An adaptive-coupling scheme is proposed to enlarge the phase shift for a wide-band locking range. The measured results exhibit an input locking range of 12.1GHz or 20.5%from 52.7 to 64.8GHz at an incident power of 0dBm. The core circuit consumes(More)
A simple, efficient CAD-oriented equivalent circuit modeling approach of frequency-dependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequency-dependent characteristics for high frequency applications using epitaxial layers on a highly doped substrate. Using the proposed modeling approach,(More)
This paper presents characterization of power LDMOS using device simulation and analytical modeling. Features of the LDMOS such as graded channel and quasi-saturation effect which result in a peculiar behavior on capacitance and nonlinear LDD resistance are analyzed and modeled using device simulation. A compact model for LDMOS is implemented in HSPICE(More)
In this paper, the scaling theory of fin field-effect transistors (FinFETs) has been established by a 3D analytical solution and numerical simulation of Poisson's equation in the channel region. Considering the impact of ionized dopant in channel and source/drain on the potential distribution, respectively, the 3D Poisson's equation is analytically solved(More)
Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its <i>O</i>(<i>N</i><sup>2</sup>) complexity for logic circuits with <i>N</i> gates. Although efforts have been made to reduce the cost at the loss of accuracy, existing methods are still unsuitable for large-scale problems. In this paper we resolve the(More)
A 2.45GHz 0.18&#x00B5;m RF CMOS Class-AB power amplifier (PA) with high linearity and output power for WLAN is presented in this paper. The proposed power amplifier is implemented with a two-stage architecture which is followed by an off-chip output matching network. To improve the linearity, an integrated diode linearization circuit provides a compensation(More)
Recently, femto-ampere current mode circuit (FCMC) implemented in modern CMOS technology is in high demand in areas like integrated bio-sensor research and production, ultra low current analysis and detection, gauging instrument design and manufacturing and etc. In this paper, on-chip circuit modules in FCMC including femto-ampere current mirror (FCM) and(More)