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This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density ParityCheck (LDPC) codes, and Reed-Solomon codes. A systematic low-complexity bit-parallel finite field multiplier design approach is proposed. This design approach is applicable to GF (2m)(More)
Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed(More)
In this paper, a sub-optimal algorithm for decoding BCH (t &#x2265; 2) turbo codes is presented. High speed VLSI decoder architecture is proposed for codes constructed over extended GF(2<sup>5</sup>). While the algorithm applies to higher order BCH product codes, it is shown that this particular block turbo codes, when decoded using the proposed algorithm,(More)
Protecting short frames using turbo coding is a challenging task because of the small interleave size and the need for transmission efficiency. In this paper, we explore possible trade-off between power consumption (estimated by the average number of iterations) and performance of turbo decoders when short frame turbo codes are used. Three encoding/decoding(More)