Zhipei Chi

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Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding archi-tectures, two types of area-efficient parallel decoding schemes are proposed. Detailed(More)
—In this comment we position the work of [1], [2] in terms of the prior literature and note that many of its results are subsumed by previous papers. I N [1], [2] modifications to the decoding of binary block Turbo codes/ Turbo product codes, as described in [3], [4], are considered. Unfortunately, the work ignores much of the existing relevant literature,(More)
In this paper, a sub-optimal algorithm for decoding BCH (t &#x2265; 2) turbo codes is presented. High speed VLSI decoder architecture is proposed for codes constructed over extended GF(2<sup>5</sup>). While the algorithm applies to higher order BCH product codes, it is shown that this particular block turbo codes, when decoded using the proposed algorithm,(More)
QR decomposition based multi-channel least square lattice (QRD-MLSL) algorithm possesses good numerical property and regularity which are attractive for VLSI implementation. But due to the presence of local recursive loop in its implementation, the algo-rithm's speed is limited to the computation time of each computation cell. In this paper, a novel(More)