Zhiguo Ge

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Power consumption is of crucial importance to embedded systems. In such systems, the instruction memory hierarchy consumes a large portion of the total energy consumption. A well designed instruction memory hierarchy can greatly decrease the energy consumption and increase performance. The performance of the instruction memory hierarchy is largely(More)
The performance of the instruction memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable instruction memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed instruction memory hierarchy consists of an instruction cache and a scratchpad(More)
—As we move into many-core era fueled by Moore's Law, it has become unprecedentedly challenging to provide the shared memory abstraction through directory-based cache coherence. The main difficulty is the high area and power overhead of the directory in tracking the presence of a memory block in all the private caches. Sparse directory offers relatively(More)
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the total energy. One of the most popular methods to reduce the energy consumption is to shut down idle cache banks. However, we observe that operating idle cache banks at a reduced(More)
The increasing density and speed of modern field programmable gate arrays offer the reconfigurable systems using them greater capability and flexibility, in particular for more complex computation. However, there remains a very important problem of how to design on a more abstract level to manage the vast hardware resource and shorten the design time. This(More)
As we enter the era of many-core, providing the shared memory abstraction through cache coherence has become progressively difficult. The de-facto standard directory-based cache coherence has been extensively studied; but it does not scale well with increasing core count. Timestamp-based hardware coherence protocols introduced recently offer an attractive(More)
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