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In this paper, we propose a new performance bound analysis of analog circuits considering process variations. We model the variations of component values as intervals measured from tested chip and manufacture processes. The new method applies a graph-based symbolic analysis and affine interval arithmetic to derive the variational transfer functions of(More)
In this paper, we propose a new time-domain performance bound analysis method for analog circuits considering process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational(More)
The shrinking technology feature size and dense large-scale integration make process variation a challenging issue directly confronting the latest design automation tools. Process variation causes severe variation in interconnect networks, including very large-scale integrated interconnect structures, such as clock trees, clock mesh, power-ground networks,(More)
Mesh circuits typically consist of many resistive links and many sources. Accurate analysis of massive mesh networks is demanding in the current integrated circuit design practice, yet their computation confronts numerous challenges. When variation is considered, mesh analysis becomes a much harder task. This paper proposes a symbolic computation technique(More)
A symbolic moment calculator for recursive moment computation of RCL interconnect networks involving resistor loops is proposed. Using the tearing technique, the network can be partitioned into a spanning tree and a set of resistor links. Special data structures for symbolic moment analysis are proposed. Applications of this structural computation(More)
A reinforcement learning based I/O management is developed for energy-efficient communication between many-core microprocessor and memory. Instead of transmitting data under a fixed large voltage-swing, an online reinforcement Q-learning algorithm is developed to perform a self-adaptive voltage-swing control of 2.5D through-silicon interposer (TSI) I/O(More)
IC design automation relies on macromodels for interconnect analysis. For simulation speed, low-order macromodels are in general preferred. Besides rational macromodels, explicit delay components e are of special interest in interconnect timing. This paper investigates new approaches to modeling interconnects in the form of multiplying a rational function(More)
Estimating the dynamic powers is crucial for power and energy efficient chip designs. With increasing variability from manufacture processes, dynamic powers can manifest significant variations due to uncertainties in device geometry and delay variations. In this paper, we propose a new statistical dynamic power estimation method considering the spatial(More)
Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing(More)