Zhi Zhu

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—In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial(More)
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transform on the input current sources to derive the analytical formula. Then, we calculate the circuit frequency response with logarithmic scale frequency components. The frequency(More)
Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC)structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer(More)
This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (ILP) formulation is proposed to identify the worst-case(More)
With the popularity of Multiple Power Domain (MPD) design, the multi-domain power network noise analysis and minimization is becoming important. This paper describes an efficient heuristic algorithm to arrange the power-up sequence in a multi-domain power network in order to minimize the noise. We present a formulation of this problem and show it is(More)
Friction stir lap welding of 7B04 aluminum alloy was conducted in the present paper, and the effect of welding speed on the defect features and mechanical performance of lap joints was investigated. The results indicate that the hook defect at the advancing side (AS) can reduce the effective thickness of the top sheet, and the sheet thinning level is(More)
In this paper, we propose an efficient approach to minimize the noise on power networks via the allocation of decoupling capacitors (decap) and controlled equivalent series resistors (ESR). The controlled-ESR is introduced to reduce the on-chip power voltage fluctuation, including both voltage drop and overshoot. We formulate an optimization problem of(More)