Zhi-Hui Kong

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In conventional digital VLSI design, one usually assumes that a usable circuit/system should always provide definite and accurate results. But in fact, such perfect operations are seldom needed in our non digital worldly experiences. The world accepts “analog computation,” which generates “good enough” results rather than totally accurate results [1]. The(More)
Content addressable memory (CAM) offers highspeed search function in a single clock cycle. Due to its parallel match-line (ML) comparison, CAM is power-hungry. Thus, robust, high-speed and low-power ML sense amplifiers are highly sought-after in CAM designs. In this paper, we introduce a parity bit that leads to 39% sensing delay reduction at a cost of less(More)
Physical unclonable function (PUF) leverages the immensely complex and irreproducible nature of physical structures to achieve device authentication and secret information storage. To enhance the security and robustness of conventional PUFs, reconfigurable physical unclonable functions (RPUFs) with dynamically refreshable challenge-response pairs (CRPs)(More)
In a Content Addressable Memory (CAM) architec­ ture, both the match-line (M L) sensing circuit and the priority encoder (PE) contribute significantly large delays during a com­ pare cycle. Meanwhile the priority encoder consumes significantly less energy when compared to the sensing circuits, i.e. rv 1 % of the overall energy consumption. Based on this(More)
The paper presents a new match line sense amplifier for Content Addressable Memory. It successfully addresses the weaknesses of contemporary designs. Extensive simulation results using a 1 V/65 nm CMOS process from STMicroelectronics have verified that the proposed sense amplifier outperforms other five contemporary designs in terms of energy consumption,(More)
A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bitand data-line capacitances. Extensive post-layout simulations,(More)