Zherui Zhang

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This paper presents a low-complexity calibrationfree digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from preand backgroundcalibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for(More)
This paper presents a novel fractional-N digital PLL structure with a digitally controlled phase interpolator (DPI) and a time-to-digital converter (TDC). In this structure, a short bit-width DPI and a short bit-width TDC are combined to achieve high phase resolution and low in-band phase noise. Moreover, since the DPI readily achieves 360° phase range and(More)
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