Zhenzhi Wu

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Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for(More)
Parallel Turbo decoding encounters conflicts during parallel data accesses because of the sequential data interleaving, and the conflicts lead to a serious decrease of throughput. Traditional conflict-free memory mapping schemes often require a huge cost of hardware, such as the area of memory, which is also a bottleneck in practical implementations. In(More)
Nowadays multi-standard wireless baseband, Convolutional Code (CC), Turbo code and LDPC code are widely applied and need to be integrated within one FEC module. Since memory occupies half or even more area of the decoder, memory sharing techniques for area saving purpose is valuable to consider. In this work, several memory merging techniques are proposed.(More)
In 5G communications, to meet the higher throughput requirement of Turbo decoding, Quadratic Permutation Polynomial (QPP) interleaver is adopted for contention-free parallel memory access. However, with the intrinsic attribute of QPP interleaver, the contention-free memory access is achieved only when the codeword length is divisible by the degree of(More)
Although deep neural networks (DNNs) are being a revolutionary power to open up the AI era, the notoriously huge hardware overhead has challenged their applications. Recently, several binary and ternary networks, in which the complex multiply-accumulate operations can be replaced by accumulations or even binary logic operations, make the on-chip training of(More)