Zhengsheng Han

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A novel integrated digital controller for buck converter based on the direct system-variable calculation is presented. Compared with linear compensators, the discrete-time direct controller is conceived to generate an additional control variable during each switching period that increases the convergence rate when system states change. An all-digital(More)
The shallow junction is used in the PDSOI technology. Unfortunately, the standard diode model maybe not suit to this PN junction. A simulation model is proposed based on the PDSOI process. The additional influence of the voltage bias of the junction to the capacitance is considered in this model and then the model is well verified by the measured data.
In this paper, the RBSOA characteristic of nanoscale Partially Narrow Mesa IGBT (PNM-IGBT) is studied by numerical simulation. Result shows that the maximum turn-off critical current of nanoscale PNM-IGBT increases about 12.3% compared with the conventional trench IGBT. The main reason is that the electric field distribution of PNM-IGBT at turn-off state is(More)
Extra charge will be generated and deposited into the cell when an energetic ion strikes the SOI SRAM. The sensitive regions will collect the deposited charge. This may upset the logic values stored in SRAM. The Geant4 is a very useful tool to simulate the process above. The GDML (Geometry Description Markup Language) file can be used to model the geometry(More)
An ion vertical striking on SOI CMOS transistor sensitive region creates an obvious large current resulting in upset of output node. Since parasitic BJT act, the single-event effect (SEE) is enhanced. In order to evaluate this effects, it is desirable to calculate critical charge (Q<inf>crit</inf>, charge collected by the drain during the entire SEE) and(More)
The structures of SOI active and passive integrated devices for RFIC applications are proposed, as well as the simplified processes. SOI RF LDMOS's, NMOS's inductors, capacitors, resistors and varactors have been integrated in the same SIMOX substrate successfully in the first experiment and key devices, including LDMOS's, NMOS's and inductors, show(More)
Dielectric isolation of silicon on insulator (SOI) technology allows circuits to be designed that have reduced single event upset effects and are free from latch-up. For these reasons, SOI technologies are well suited for space applications. In this paper, we investigated both single event upset (SEU) and single event latch-up (SEL) effects of 512k bits(More)
3D fully-depleted silicon-on-insulator (FDSOI) n-channel transistor model is constructed by the accurate calibration between process information from OKI and Synopsys TCAD tool. Single-event-effect (SEE) simulations are conducted based on the 3D model to evaluate the collected charge from different heavy ion strike locations. The channel is the most SEE(More)
The shallow trench isolation (STI) y-stress effect on deep submicron PDSOI MOSFETs was studied. Instance parameters SAy, SBy and model parameters a1, a2, b1, b2 were proposed to build a compact model for this effect. This model can be easily implemented in the SOI MOSFET compact model like BSIMSOI model. By using this model, we can simulate the STI y-stress(More)