Zhengsheng Han

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Extra charge will be generated and deposited into the cell when an energetic ion strikes the SOI SRAM. The sensitive regions will collect the deposited charge. This may upset the logic values stored in SRAM. The Geant4 is a very useful tool to simulate the process above. The GDML (Geometry Description Markup Language) file can be used to model the geometry(More)
A novel integrated digital controller for buck converter based on the direct system-variable calculation is presented. Compared with linear compensators, the discrete-time direct controller is conceived to generate an additional control variable during each switching period that increases the convergence rate when system states change. An all-digital(More)
3D fully-depleted silicon-on-insulator (FDSOI) n-channel transistor model is constructed by the accurate calibration between process information from OKI and Synopsys TCAD tool. Single-event-effect (SEE) simulations are conducted based on the 3D model to evaluate the collected charge from different heavy ion strike locations. The channel is the most SEE(More)
The shallow trench isolation (STI) y-stress effect on deep submicron PDSOI MOSFETs was studied. Instance parameters SAy, SBy and model parameters a1, a2, b1, b2 were proposed to build a compact model for this effect. This model can be easily implemented in the SOI MOSFET compact model like BSIMSOI model. By using this model, we can simulate the STI y-stress(More)
The shallow source and drain is used in the PDSOI technology. Unfortunately, most of the standard commercial SOI MOSFET model is for the device with deep source and drain, the necessity of the new models for this device arises. A simulation model is proposed based on the 0.13μm PDSOI process developed by the Institute of Microelectronics of the(More)
The structures of SOI active and passive integrated devices for RFIC applications are proposed, as well as the simplified processes. SOI RF LDMOS's, NMOS's inductors, capacitors, resistors and varactors have been integrated in the same SIMOX substrate successfully in the first experiment and key devices, including LDMOS's, NMOS's and inductors, show(More)
Single event transient (SET) issues become a primary concern in modern CMOS logic circuits. The possibility of soft errors due to the propagation of SETs is increasing, and becomes a significant reliability challenge. In this paper, single event transients in a 100 series 0.18 μm partially-depleted Silicon-On-Insulator (PDSOI) CMOS inverter chain are(More)
We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35µm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
An ion vertical striking on SOI CMOS transistor sensitive region creates an obvious large current resulting in upset of output node. Since parasitic BJT act, the single-event effect (SEE) is enhanced. In order to evaluate this effects, it is desirable to calculate critical charge (Q<inf>crit</inf>, charge collected by the drain during the entire SEE) and(More)
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