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Computer architecture is transiting from the multicore era into the heterogeneous era in which heterogeneous architectures use on-chip networks to access shared resources and how a network is configured will likely have a significant impact on overall performance and power consumption. Recently, heterogeneous network on chip (NoC) has been proposed not only(More)
A NoC is a critical shared resource among these concurrently-executing applications, significantly affecting system performance, and energy efficiency. In this paper, we propose B<sup>2</sup>L, a buffered and bufferless hybrid NoC design that can satisfy application's performance requirements, while the system's energy consumption is minimized. This can be(More)
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