Zhang Yigang

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
Asynchronous serial communications are frequently used for data exchange between test system and the peripheral to be tested in research and development of automatic test systems. However, in most conditions, a test system with a single CPU can not meet the demand of multi-channel asynchronous serial communications. In the design of an automatic test system(More)
Based on the detailed analysis of M-Module specification and PCI specification, this thesis design a kind of M-Module carrier which based on PCI bus. The design use FPGA as core controller in the design of hardware to decrease difficulty and cost. The design used IP core to control PCI interface and developed firmware for M-Module interface. This design(More)
Timing sequence test is a core part for missile ground testing, the results directly determine whether the missile can be well launched. A specialized CPCI timing sequence testing system for missile is presented in this paper, which is able to complete the sequence test of tail boot, gesture controller, sequence circuit, instant flight for both equivalent(More)
In digital signal processing area, Field Programmable Gate Array (FPGA) is becoming the ideal platform of Finite Impulse Response (FIR) filter design with its excellent features. However, traditional development method is difficult and costs a lot of manpower and time. In this paper, we accomplish the FIR digital filter design with high-level synthesis(More)
Rapid satellite deployment is the primary goal of Space Plug-and-Play Architecture (SPA), the Appliqué Sensor Interface Module (ASIM) is necessary for Non-SPA compliant components to be converted into SPA compliant. Focusing on current ASIM not supporting power hot swap, a SPA-S (SpaceWire) ASIM with power hot swap capability was designed and(More)
This paper proposes the idea of designing an testing platform for seeker to the core of embedded system. Through generalizing the testing requirements, the adapting interface of data acquisition, storage, transmission and displaying are devised reasonably. The dual core structure of ARM9 and FPGA is applied in the hardware design, and the software adopts(More)
  • 1