Zhang Chun

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
A modified DSP architecture, to accelerate motion estimation (ME) algorithms, is presented in this paper. The proposed SIMD and VLIW architecture is a trade-off between ASIC implementation and DSP implementation of ME, which can perform subtract, absolute and add (SAA.) operations on 8 pixels and fetch 8 new pixels from memory at the same time. A flexible(More)
Due to the weak signal energy of the backscatter link, traditional RFID communication is easily affected by noises, interferences, and interceptions from the environment. To solve the problem, a novel passive UHF RFID tag baseband processor enhanced with spread spectrum technique is presented in this paper. In addition, power-saving strategies are proposed(More)
A digital tuning self-calibrating on-chip termination resistor for high-speed SerDes is presented in this paper. An offchip reference resistor is used to adjust the on-chip resistor automatically through feedback. SAR logic is used for tuning, which shorts the tuning time. Special analog design is used to eliminate the offset of circuit and reduce the power(More)
Motion estimation (ME) consumes the majority of computation capacity of a DSP in video compression applications. A modified DSP architecture, to accelerate ME algorithms, is presented in this paper. The proposed SIMD and VLIW architecture is a trade-off between ASIC implementation and DSP implementation of ME, which can perform subtract, absolute and add(More)
Bit stream coding plays an important role in image and video compressing standards. This paper presents a H.264 baseline profile bit-stream decoding solution based on application specific processor. The bit-stream decoder hardware is integrated into the RISC processor as a sub-module of its ALU. It can decode one symbol every clock cycle through one(More)
  • 1