Zezhong Yang

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A local bit line (LBL) based on forced-keeper technique for on-chip memories is proposed in this paper. The keeper transistor is forced to be turned off adaptively to decrease the leakage current and the contention current to achieve high performance. With SMIC 65 nm technology, the simulation results show that the proposed LBL chosen by the row decoder(More)
This paper presents a CMOS technology compatible non-volatile 8T SRAM called NV SRAM. NV SRAM works as conventional 8T SRAM to keep high speed and high noise margin in work mode; in sleep mode, the data is kept in non-volatile part and the power supply is switched off, thereby minimizing the leakage energy without data loss. Based on 65 nm SMIC Technology,(More)
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