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In this paper, a quasi-multiple medium (QMM) method based on the direct boundary element method (BEM) is presented to extract the capacitance of three-dimensional (3-D) very large scale integration interconnects with multiple dielectrics. QMM decomposes each dielectric layer into a few fictitious medium blocks, and generates an overall coefficient matrix(More)
This paper gives an improved single-layer potential formula for extracting the parasitic capacitance of multiple conductors, embedded in the infinite or finite dielectrics, based on the MultiPole Accelerated (MPA) method. In fact, many capacitors should be considered to be bounded by a finite region. This indicates that the improvement is necessary to raise(More)
A new resistance simulator for extraction of the parasitic parameters from VLSI layout is presented. The calculation of resistor network is based on the boundary element method (BEM). The computational results indicate that the BEM has an advantage over the finite difference method (FDM) and the finite element method (FEM). Since only discretized equations(More)
An efficient method is proposed to consider the process variations with spatial correlation, for chip-level capacitance extraction based on the window technique. In each window, an efficient technique of Hermite polynomial collocation (HPC) is presented to extract the statistical capacitance. The capacitance covariances between windows are then calculated(More)
As shown in literatures, partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, because the partial reluctance exhibits much better locality than partial inductance. However, most previous works on reluctance extraction did not take high frequency effect into account and were not efficient enough for 3-D complex(More)
The idea of Appel's hierarchical algorithm handling the many-body problem is implemented in the direct boundary element method (BEM) for computation of 3D VLSI parasitic capacitance. Both the electric potential and normal electric field intensity on the boundary are involved, so it can be much easier to handle problems with multiple dielectrics and finite(More)
Partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, for its better locality than the partial inductance. But few previous works on reluctance extraction took the high frequency effect into account or were efficient enough for 3D complex structure. In this paper, a new reluctance extraction algorithm is presented(More)
Since the early 1950s, microwave circuits have evolved from discrete circuits to planar integrated circuits, then to multilayered and three-dimensional integrated circuits. With the increased circuit density, the multiconductor line in multilayered dielectric media has become the major form of the transmission line or interconnect. Multilayered routing(More)
The high frequency resistance and inductance of the 3-D complex interconnect structures can be calculated by solving an eddy current electromagnetic problem. In this paper, a model for charactering such a 3-D eddy current problem is proposed, in which the electromagnetic fields in both the conducting and non-conducting regions are described in terms of the(More)