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The High-Speed Simulator (HSS) is a fast and flexible system for gate-level fault simulation. Originally limited to combinational logic, it is being extended to handle sequential logic. It may also prove useful as a functional simulator. The speed of HSS is obtained by converting the cycle-free portions of a circuit into optimized machine code for a(More)
With the advent of VLSI, testing has become one of the most costly, complicated, and time consuming problems. The method of syndrometesting is applicable toward VILSI testing since it does not require test generation and fault simulation. It can also be considered as a vehicle for self-testing. In order to employ syndrome-testing in VLSI, we electronically(More)
We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient(More)
An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined. Implementing this algorithm yields an efficient tool for custom VLSI circuit design verification and fault simulation. Modeling of circuits under this environment is defined, including the analysis of the algorithm's performance for some general circuit(More)