Zbigniew Jachna

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The paper describes two time-interval generators based on the phase shifting method. The first one utilizes the digital clock manager units integrated in a field programmable gate array (FPGA) device and has jitter below 65 ps (rms) over the range of 4 ns-50 ms, while the second one utilizes a separate direct digital synthesizer and has jitter below 15 ps(More)
This paper presents the design, architecture, operation, and test results of a high precision time interval and frequency counter made as a small, portable instrument with USB interface. Thanks to the use of advanced time interpolators integrated in a CMOS chip, the precision (standard deviation) below 35 ps was obtained at measured time interval from 0 to(More)
We present the design and test results of a new four-channel, precise, low-cost, time-event recorder. The measurement part of the recorder combines timestamp method with two-stage in-period interpolation and is implemented in off-the-shelf Spartan-6 FPGA device manufactured by Xilinx in 45 nm CMOS process. The designed device allows for simultaneous(More)
We present the design, operation and test results of a time-to-digital converter based on multiphase clock and implemented in Kintex-7 FPGA (Xilinx). Proposed solution involves a Vernier delay line constructed with the use of Look-Up Tables and interconnect resources. Taking advantage of rising amount of available interconnect resources in modern FPGA(More)
General functional decomposition has important applications in many fields of modern engineering and science. However, it is mainly perceived as a method of logic synthesis for implementation of Boolean functions into FPGAbased architectures. In this paper, an application of functional decomposition in other fields of modern engineering is presented. The(More)
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