Zaiping Zeng

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We compute the electron and hole mobilities in Trigate and gate-all-around silicon nanowires (SiNWs) within the nonequilibrium Green’s Function framework. We then derive a simple model for the dependence of the mobility on the SiNW width and height. This model interpolates between the square SiNW and thin film limits. In order to provide a complete(More)
We hereby present a study of electron mobility in Tri-gate SOI Nanowire (TGNW) transistors in a wide range of temperature from 20K up to 425K. We compared the temperature dependence for different values of the NW cross-section (width and height) and different crystallographic orientations of the conduction channel. We demonstrate that the electron mobility(More)
Multi-gate transistors have attracted considerable attention as a way to overcome the scaling issues of planar MOSFETs. Although the effects of structural confinement on the carrier mobilities have been discussed extensively, the transition from silicon thin films to silicon nanowires (SiNWs) has been little investigated. In this contribution, we perform(More)
The introduction of a high-K/metal gate stack in metal-oxide-Semiconductor field-effect transistors can cause a significant degradation of the mobility, especially at weak inversion densities. This degradation is commonly ascribed to remote Coulomb scattering (RCS, i.e., charges trapped at the SiO<sub>2</sub>/HfO<sub>2</sub> interface). However, very large(More)
GAA nanowires (NW) transistors are promising candidates for sub 10 nm technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. Horizontally stacked they are a natural extension of today's mainstream technology. Considering enlarged NWs in Nanosheets (NS) allows to target the best compromise in power and(More)
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