• Publications
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Fast Simulation of Pipeline in ASIP Simulators
  • Z. Prikryl
  • Computer Science
  • 15th International Microprocessor Test and…
  • 15 December 2014
TLDR
A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Expand
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Fast Cycle-Accurate Interpreted Simulation
TLDR
The area of hardware/software co-design deals with the design of ASIPs (Application Specific Instruction-set Processors) because they often create the core of an embedded system. Expand
  • 8
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Automated Functional Verification of Application Specific Instruction-set Processors
TLDR
We introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Expand
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Advanced Methods of Microprocessor Simulation
Embedded systems have become indivisible part of our everyday activities. They are dedicated devices performing a particular job. A computing core of more complicated embedded systems is formed byExpand
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Retargetable multi-level debugging in HW/SW codesign
TLDR
We present the concept of an automatically generated multi-level retargetable debugger that allows debugging of multiprocessor systems. Expand
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Fast just-in-time translated simulator for ASIP design
TLDR
In this paper, we present the concept of automatically generated just-in-time translated simulator with profiling capabilities. Expand
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Fast Translated Simulation of ASIPs
TLDR
This paper introduces a special simulation type that exploits information from a target C compiler to generate a simulator based on a processor description. Expand
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Fast cycle-accurate compiled simulation
TLDR
We present a cycle-accurate compiled simulation for embedded systems, which guarantees independence on a host platform, including very good performance and precision. Expand
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Generated Cycle-Accurate Profiler for C Language
TLDR
A way to generate cycle-accurate profiler for C language from a processor model described with an architecture description language is proposed. Expand
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Design and Simulation of High Performance Parallel Architectures Using the ISAC Language
TLDR
This article presents utilization of new extensions for existing architecture description language ISAC for fast prototyping and testing of parallel based systems and processors. Expand
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