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A two stage fully integrated low-noise amplifier has been developed for 4.9-6 GHz WLAN applications. This circuit was realized in a 0.35 /spl mu/m SiGe BiCMOS process and packaged in a low cost plastic VFQFPN package. The circuit operates over a wide band (4.9-6 GHz) and draws 13.2 mA from 2.0 V supply. It exhibits a noise figure of 3.9 dB and a gain of(More)
At millimeter wave (MMW) frequencies, high data rate applications such as kiosk downloading or Wireless HDMI require low cost and low power Systems on Chip (SoC) to address mass-market products and consumer expectations. Along with the developments of 60 GHz chipset solutions, low-cost antennas and package costs are obviously key factors to succeed in large(More)
Ball Grid Array packaging for integrated circuits permits to address most standard electronics applications with recognized and proven advantages of low cost, high volume capability, design flexibility & electrical/thermal/mechanical performances. However, standard BGA package technology approach, i.e. cost driven technology selection in other words, is(More)
Almost every electronic device is sensitive to electrostatic discharges. The charged device model (CDM) is today used by the industry to characterize the electrostatic discharge events that occurs in an automated industrial environment. Based on this model, the JEDEC and ESDA give some standards that, with specific test equipment, rank the electronic device(More)
The scope of this article is concerning the electrical modeling tools used for the package parasitic extraction. Many 3D electrical modeling tools are on the market today enabling different type of electrical models to represent the electrical behavior of the packages. Semi-conductor companies are using many of them to address a wide range of applications,(More)
This paper has shown interesting decoupling solutions of PDNs, when they should be employed and what tradeoff between electrical performance and cost should be considered. It has shown through a concrete example the PDN decoupling strategy done on a typical set top box product and its validation through measurement and simulation. Finally it has briefly(More)
Today, new technologies in packaging assembly method (e.g. Copper Pillar FC bumping, 3D, etc...) are generating many new design rules. Historically the Wire Bond assembly was largely used and mastered but due to new technological breakthrough in the Flip Chip assembly method (eg Copper Pillar bumping) the trend is reversed and most of ST projects are now(More)
This paper aims to make a full evaluation of inductor performances integrated in multi layer FO-WLP technology. Technology interest for radio frequency passives is first discussed. The inductor offer, composed of four different inductor families, is described including more than 200 different inductors that were fabricated. Measurements exhibit promising(More)
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