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The Kalray MPPA®-256 processor (Multi-Purpose Processing Array) integrates 256 processing engine (PE) cores and 32 resource management (RM) cores on a single 28nm CMOS chip. These cores are distributed across 16 compute clusters and 4 I/O subsystems. On-chip communications and synchronization are supported by an explicitly routed dual data &(More)
The emerging 4G wireless telecommunication technology poses two inevitable constraints for the chipset design: a high level of integration and algorithm complexity. But even though nanomet-ric CMOS technologies make it possible to integrate the required hardware resources into a single chip, enormous difficulties arise for the on-chip interconnections and(More)
The SIDRAH project proposes a software package to enable spontaneous collaboration between wireless devices. Networked devices temporarily form a group, called a SIDRAH community, where they offer services to each others. We propose a complete solution, from template services down to wireless protocol stacks to realize this. We face two major issues: 1/ How(More)
EUROSERVER is a collaborative project that aims to dramatically improve data centre energy-efficiency, cost, and software efficiency. It is addressing these important challenges through the coordinated application of several key recent innovations: 64-bit ARM cores, 3D heterogeneous silicon-on-silicon integration, and fully-depleted silicon-on-insulator (FD(More)
Whereas the computing power of DSP or general-purpose processors was sufficient for 3G baseband telecommunication algorithms, stringent timing constraints of 4G wireless telecommunication systems require computing-intensive data-driven architectures. Managing the complexity of these systems within the energy constraints of a mobile terminal is becoming a(More)
Instead of a single circuit dedicated to a particular physical (PHY) layer standard, a Software Defined Radio (SDR) platform embeds several hardware accelerators which enable it to support different modulation schemes. In this study we propose an architecture for a SDR PHY layer based on the Virtual Machine (VM) concept. Once a program is compiled in a(More)