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A low-power dynamic reconfigurable FFT fabric is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for System on Chip applications. The system can be configured as 16, 32, 64, 128, 256, 512 and 1024-point FFT. Compared with a conventional ASIC FFT processor, this FFT fabric is characterized by having dynamic(More)
—A novel low-power reconfigurable FFT processor is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for System on Chip applications. The system can be configured as from 16-point to 1024-point FFT. Flexibility is added to address generation block, coefficient memory block and data memory block. Two switch blocks are(More)
  • R Ruk, Enas K Sere, Y Zhao
  • 2007
We present an outline of a method for formal derivation of asyn-chronous VLSI circuits. The proposed method focuses on transformational style of the design and it uses techniques familiar from the construction of parallel programs. Reenement calculus and action systems are used as a framework for the design process. As a case study we look at the derivation(More)
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