Yutaka Tashiro

Learn More
This paper presents a design for a real-time MPEG2 SP@ML video-encoder chip set. Its main features are: hardware/software partitioning based on a software en-coder analysis, and a pifieline architecture where hardware and software interact closely and smoothly. We use a hardware/software concurrent design technique with fast verification to avoid major(More)
This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated(More)
This article presents some examples of video content delivery and two-way video communication services and describes current trends in the digital media technology supporting these services. It also describes NTT's research efforts in subjects such as video coding and introduces our vision of business services that combine high-quality secure video delivery(More)
  • 1