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—This paper describes a prototype software defined radio (SDR) transceiver on a distributed and heterogeneous hybrid programmable architecture; it consists of a central processing unit (CPU), digital signal processors (DSPs), and pre/ postprocessors (PPPs), and supports both Personal Handy Phone System (PHS), and IEEE 802.11 wireless local area network(More)
Since the proposed timing recovery circuit can handle relatively large frequency offsets, manufacturing costs are quite low. To achieve both accurate timing synchronization and high tracking ability, a 2-stage timing recovery circuit is proposed, composed of an acquisition circuit and a tracking circuit. The proposed circuit has the two major features: (1)(More)
In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based decimators. A multiplier less CIC decimator has been used to reduce the cost by reducing the multiplier requirement. Two(More)
―A software defined radio (SDR) prototype based on a multiprocessor architecture (MPA) is developed. Software for Japanese personal handy phone system (PHS) of a 2G mobile system, and IEEE802.11 wireless LAN, which has much wider bandwidth than the 2G systems, is successfully implemented. Newly developed flexible-rate pre-/post-processor (FR-PPP) achieves(More)
Drastic improvements in transmission rate and system capacity are required towards 5th generation mobile communications (5G). One promising approach, utilizing the millimeter wave band for its rich spectrum resources, suffers area coverage shortfalls due to its large propagation loss. Fortunately, massive multiple-input multiple-output (MIMO) can offset(More)