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A novel method for the extraction of the lateral position of border traps in nanoscale MOSFETs is presented. Using technology computer-aided design (TCAD) simulations, we demonstrate that the dependence of the trap-induced threshold voltage shift on the drain bias is more sensitive to the lateral trap position than to the impact of random dopants. Based on(More)
We propose a new method to determine the lateral trap position in ultra-scaled MOSFETs with a precision of less than 1nm. The method is based on an analytical model which links the surface potential in the presence of a discrete trap to the drain voltage. We demonstrate that the dependence between the surface potential in the damaged region of the channel(More)
—We report a first study of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs). Our results show that HCD in GFETs is recoverable, similarly to the bias-temperature instability (BTI). Depending on the top gate bias polarity, the presence of HCD may either accelerate or suppress BTI. Contrary to BTI, which mainly results in a change(More)
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