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System level design for many-core chips includes general system architecture design, MPSoC design as a set of nodes and their interconnection. It requires adequate models and methodology to estimate MPSoC interconnection characteristics in complexity and power consumption to make decisions at the system level design stage of an MPSoC project. To determine(More)
The paper presents the architecture of the high performance prospective processing SoC with communication protocol SpaceWire as the Next Generation DSP Multi-core Processor for Onboard Payload Data Processing Applications. DSP Multi-core processor continues processors road map which begins from dual cores processor 0.25-u MC-24R from (chipset " MCFLIGHT ")(More)
An ability of faults mitigation becomes one of the main requirements for network-on-chip (NoC) embedded systems that are manufactured with thin design rules. Other requirements are for area, power consumption and QoS. Altogether these requirements lead to inconsistencies in NoC development process. In this paper we discuss approaches for resolving this(More)
Nowadays embedded systems solve tasks in various domains (avionics, space industry, automotive, mobile devices, domestic appliances and so on). Moreover, these tasks are composed in various concepts: IoT, cyber-physical systems etc. Different classes of problems of the market and its needs make manufacturers of embedded systems to design heterogeneous(More)