Yunseung Shin

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An experimental 16-Mbit CMOS DRAM with die size of 8.52 X18.4 mm<sup>2</sup> has been developed. A trenched and saddled stack capacitor (TSSC) cell was invented, and storage capacitance of 30fF was obtained in a cell size of 1.65 x 3.339 ?spl mu/m<sup>2</sup>. Peak-current noise on the power buses during the sense-amplifier latching is suppressed by(More)
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