Yuko Hanaoka

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For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called “chip-level TSV integration”) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation(More)
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