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The non-local band to band tunneling model developed and implemented into the three-dimensional device simulator by the authors is evaluated for the tunnel-FET modeling focused on device geometry effects. Measured characteristics of SOI, Fin, and parallel-plate silicon tunnel FETs fabricated by the authors are compared with simulations based on the(More)
Polycrystalline-silicon (poly-Si) and crystalline-silicon (crystal-Si) channel FinFET CMOS inverters were successfully fabricated and the variations of threshold voltage (V<sub>t</sub>) for their individual n- and p-channel transistors and the logic gate V<sub>t</sub> (V<sub>Thc</sub>) for the inverters were systematically investigated. It was found that(More)
Tunnel FETs with vertical tunnel paths are fabricated and successfully modeled by the nonlocal band to band tunneling model. Although enhancement of ON currents are obtained by longer source gate overlap lengths, the increase of the ON current is less than proportional to the overlap lengths, because of non-uniformity of the band to band tunneling(More)
The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al 2 O 3 and SiO 2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V t) variability, and the memory characteristics have been comparatively(More)