The non-local band to band tunneling model developed and implemented into the three-dimensional device simulator by the authors is evaluated for the tunnel-FET modeling focused on device geometry effects. Measured characteristics of SOI, Fin, and parallel-plate silicon tunnel FETs fabricated by the authors are compared with simulations based on the… (More)
Acknowledgments Technical support by the ICAN, AIST 1 Outline Background of this study-Why "higher-k" gate stack-Our strategy Purpose Experimental procedure Results and discussion Summary 2 1.
Tunnel FETs with vertical tunnel paths are fabricated and successfully modeled by the nonlocal band to band tunneling model. Although enhancement of ON currents are obtained by longer source gate overlap lengths, the increase of the ON current is less than proportional to the overlap lengths, because of non-uniformity of the band to band tunneling… (More)
Polycrystalline-silicon (poly-Si) and crystalline-silicon (crystal-Si) channel FinFET CMOS inverters were successfully fabricated and the variations of threshold voltage (V<sub>t</sub>) for their individual n- and p-channel transistors and the logic gate V<sub>t</sub> (V<sub>Thc</sub>) for the inverters were systematically investigated. It was found that… (More)
A threshold voltage (V th) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the V th of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the V th… (More)