—In this paper, high-frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. A subcircuit RF model incorporating the HF effects of parasitics is presented. This model is compared with the measured data for both parameter and characteristics. Good model accuracy is achieved against measurements… (More)
Acknowledgment: The development of BSIM3v3.2 benefited from the input of many BSIM3 users, especially the Compact Model Council (CMC) member companies. TSMC for their valuable assistance in identifying the desirable modifications and testing of the new model. their guidance and support.
In this paper, we discuss some important issues in MOSFET modeling for radio-frequency (RF) integrated-circuit (IC) design. We start with the introduction of the basics of RF modeling. A simple sub-circuit model is presented with comparisons of the data for both y parameter and f T characteristics. Good model accuracy is achieved against the measurements… (More)
In this paper, high frequency (HF) AC and noise modeling of MOSFETs for low noise, radio frequency (RF) integrated circuit (IC) design are discussed. Scalable parasitic model and the Non-Quasi-Static (NQS) model are discussed and verified with the measured data. For the noise modeling, extracted noise sources of MOSFETs in 0.18 µ µm CMOS process and from RF… (More)
Four 20 ns molecular dynamics simulations have been performed with two counterions, K+ or Na+, at two water contents, 15 or 20 H2O per nucleotide. A hexagonal simulation cell comprised of three identical DNA decamers [d(5'-ATGCAGTCAG) x d(5'-TGACTGCATC)] with periodic boundary condition along the DNA helix was used. The simulation setup mimics the DNA state… (More)
Digital designers to take over the world when analog designers produce 10 Gbps 18-bit data converters that attach to antennas." This may be a dream, but many next-generation analog systems need high resolution (>12 bits) circuits that run at higher sampling rates. PLL designers can push the speed envelope, but what about other analog blocks? Has scaling… (More)
—This paper reports a new nanocrystal quantum-dot (NC-QD)-based tunable on-chip electrostatic discharge (ESD) protection mechanism and structures. Experiments validated the pro-grammable ESD protection concept. Prototype structures achieved an adjustable ESD triggering voltage range of 2.5 V, very fast response to ESD transients of rising time t r ∼ 100 ps… (More)