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The electrical behavior of shallow silicide-to-silicon ohmic contacts has been evaluated for lateral dimensions to 50 nm. Trench-isolated series resistance test structures were fabricated using… Continue Reading
Fabrication of CMOS devices with feature sizes on the order of 100 nm will require junction depths of less than 70 nm in order to control short-channel effects. Fully-scaled 100x100 nm/sup 2/… Continue Reading