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Self-aligned double patterning (SADP) lithography is a promising technology which can reduce the overlay and print 2D features for sub-32nm process. Yet, how to decompose a layout to minimize the overlay and perform hot spot detection is still an open problem. In this paper, we present an algorithm that can optimally solve the SADP decomposition problem.(More)
Double patterning lithography (DPL) technologies have become a must for today's sub-32nm technology nodes. There are two leading DPL technologies: self-aligned double patterning (SADP) and litho-etch-litho-etch (LELE). Among these two DPL technologies, SADP has the significant advantage over LELE in its ability to avoid overlay, making it the likely DPL(More)
Self-aligned double patterning (SADP) lithography is a leading technology for 10<i>nm</i> node Metal layer fabrication. In order to achieve successful decomposition, SADP-compliant design becomes a necessity. Spacer-Is-Dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. This paper makes a careful study on the challenges(More)
At the 10 nm technology node, the contact layers of integrated circuits (IC) designs are too dense to be printed by single exposure using 193 nm immersion (193<i>i</i>) lithography. Among all the emerging patterning approaches, block copolymer directed self-assembly (DSA) is a promising candidate with high throughput and low cost for sub-20 nm features.(More)
Triple patterning lithography (TPL) has been recognized as one of the most promising techniques for 14/10nm technology node. There are various concerns for TPL decompositions. For standard cell based designs, assigning the same pattern for the same type of cells is a desired property for TPL decomposition. It is more robust for process variations and gives(More)
—FinFET transistors have great advantages over traditional planar MOSFET transistors in high performance and low power applications. Major foundries are adopting the Fin-FET technology for CMOS semiconductor device fabrication in the 16 nm technology node and beyond. Edge device degradation is among the major challenges for the FinFET process. To avoid such(More)
Self-aligned double patterning is one of the most promising double patterning techniques for sub-20nm nodes. As in any multiple patterning techniques, layout decomposition is the most important problem. In SADP decomposition, overlay is among the most primary concerns. Most of the existing works target at minimizing the overall overlay, while others totally(More)
Triple patterning lithography (TPL) has been recognized as one of the most promising candidates for 14/10nm technology node. Apart from obtaining legal TPL decompositions, various concerns have been raised by the designers, among them consistently assigning the same pattern for the same type of standard cells and balancing the usage of the three masks are(More)