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A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed. The architecture is designed based on a highly parallel CRC algorithm. The algorithm first divides a given message with any length into bytes. Then it performs CRC computation using lookup tables among the divided bytes in parallel. At last,(More)
VLSI (Very Large-Scale Integration) designs for communication coding and decoding should, in general, provide high throughput, achieve low computing latency, occupy low silicon cost, and handle multiple bit manipulation algorithms. Application-Specific Instruction-set Processor (ASIP) is an optimized solution to fulfill all these requirements. This paper(More)
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