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PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
TLDR
This work proposes a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory, and distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving.
View on ACM
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator
TLDR
DRISA, a DRAM-based Reconfigurable In-Situ Accelerator architecture, is proposed to provide both powerful computing capability and large memory capacity/bandwidth to address the memory wall problem in traditional von Neumann architecture.
View on ACM
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories
TLDR
This work proposes Pinatubo, a Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations, which redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows very efficiently, and support one-step multi-row operations.
View on ACM
Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices
TLDR
A SWAP-based Bidirectional heuristic search algorithm (SABRE) is proposed, applicable to NISQ devices with arbitrary connections between qubits, which outperforms the best known algorithm with exponential speedup and comparable or better results on various benchmarks.
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Overcoming the challenges of crossbar resistive memory architectures
TLDR
The architecture improves the performance of a system using ReRAM-based main memory by about 44% over a conservative baseline and 14% over an aggressive baseline on average, and has less than 10% performance degradation compared to an ideal DRAM-only system.
View on IEEE
HyGCN: A GCN Accelerator with Hybrid Architecture
TLDR
This work describes the hybrid execution patterns of GCNs on Intel Xeon CPU and proposes a hardware design with two efficient processing engines to alleviate the irregularity of Aggregation phase and leverage the regularity of Combination phase, and designs a GCN accelerator using a hybrid architecture to efficiently perform GCNs.
View on IEEE
Architecture exploration for ambient energy harvesting nonvolatile processors
TLDR
The simulation platform in this paper is calibrated using measured results from a fabricated nonvolatile processor and used to explore the design space for a nonVolatile processor with different architectures, different input power sources, and policies for maximizing forward progress.
View on IEEE
Cambricon: An Instruction Set Architecture for Neural Networks
TLDR
This paper proposes a novel domain-specific Instruction Set Architecture (ISA) for NN accelerators, called Cambricon, which is a load-store architecture that integrates scalar, vector, matrix, logical, data transfer, and control instructions, based on a comprehensive analysis of existing NN techniques.
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DESTINY: A tool for modeling emerging 3D NVM and eDRAM caches
TLDR
DESTINY is presented, a microarchitecture-level tool for modeling 3D (and 2D) cache designs using SRAM, embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM) and phase change RAM (PCM), and has been validated against industrial cache prototypes.
View on IEEE
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey
TLDR
This article reviews the mainstream compression approaches such as compact model, tensor decomposition, data quantization, and network sparsification, and answers the question of how to leverage these methods in the design of neural network accelerators and present the state-of-the-art hardware architectures.
View on IEEE
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