Yuan C. Chou

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Ab ¡ stract T ¢ his pape r de monstrates how an Ins truction Path Co-pr £ ocessor (I-COP) can be efficiently implemented using the P ¤ ipeRench reconfigurable architecture. An I-COP is a pro-gr ¥ ammable on-chip coprocessor that operates on the core pr £ ocessor's instructions to tr ansform them into a new format t ¦ hat can be more efficiently executed.(More)
Dextromethorphan ((+)-3-methoxy-N-methylmorphinan, DM) has been shown to have both anticonvulsant and neuroprotective effects. The mechanisms of these CNS effects of DM have been suggested to be associated with the low-affinity, noncompetitive, N-methyl-d-aspartate (NMDA) antagonism of DM and/or the high-affinity DM/sigma receptors. DM is largely(More)
Previous study demonstrated that, in hippocampal neuron/glia mixed cultures, glucocorticoids (GCs) enhanced extracellular overflow of [3H]D-aspartate [3H]D-Asp) by decreasing its uptake, thereby aggravating cell death during cyanide-induced ischemia. Since neuronal and glial cells respond to ischemic insult and GC differently, this study further evaluated(More)
The effects of hypoxia on rat locus coeruleus (LC) neurons were investigated by intracellular recording from in vitro brain slices. In response to a brief exposure to hypoxic medium (2-5 min), equilibrated with 95% N2 - 5% CO2, two populations of cells could be distinguished, type 1 neurons (61%), showing hyperpolarization (9.3 +/- 0.4 mV, n = 125) and(More)
This paper presents the concept of dynamic control independence (DCl) and shows how it can be detected and exploited in an out-of-order superscalar processor to reduce the performance penalties of branch mispredictions. We show how DCI can be leveraged during branch misprediction recovery to reduce the number of instructions squashed on a misprediction as(More)
<italic>This paper presents the concept of an Instruction Path Coprocessor (I-COP), which is a programmable on-chip coprocessor, with its own mini-instruction set, that operates on the core processor's instructions to transform them into an internal format that can be more efficiently executed. It is located off the critical path of the core processor to(More)
Simultaneous multithreading is a recently proposed technique in which instructions from multiple threads are dispatched and/or issued concurrently in every clock cycle. This technique has been claimed to improve the latency of multithreaded programs and the throughput of multiprogrammed workloads with a minimal increase in hardware complexity. This paper(More)
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