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In this paper, we introduce a real-time, dual independent output MPEG-2 transport stream (TS) processor designed specific for the China HDTV testing zones. The processor is a single piece of equipment, of which the core functions are realized in FPGA and DSP. Key technologies include a program clock reference (PCR) correction and a packets controller, which(More)
This paper presents a joint bit allocation strategy for parallel HDTV video encoders. The basic idea is to partition a HDTV picture into six smaller sub-pictures, then compress each sub-picture using a cheap MPEG-2 MP@ML encoder. Without coordination among sub-encoders, these encoded sub-pictures may have unequal picture qualities. To maintain a uniform(More)
A data transmission/reception circuit based on parallel FIFO storage structure is introduced. It is used as a video data testing source for an HDTV encoder or used for encoded data test and analysis. It is designed for being inserted in a PC's AT bus. Under the control of a PC, it can transmit or receive data at very high speed. Its function, structure,(More)
The wireless channel is highly time−varying where packet losses often occur during the fading or lossy handovers. In order to avoid unaccepted quality degradation of video streaming over 3G cellular networks, we propose and analyze a novel client−driven scalable cross−layer (CSC) retransmission scheme. Considering the perceptual importance of different(More)
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