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We have developed a power-aware CMOS technology featuring variable V/sub DD/ and back-bias control. Three typical operation modes are defined: high-speed mode (V/sub DD/ = 1.2V, V/sub B/ = 0V), nominal mode (V/sub DD/ = 0.9V, V/sub B/ = -0.5V) and power-save mode (V/sub DD/ = 0.6V, V/sub B/ = -2.0V). Compared with nominal mode, one and a half order of(More)
We have developed 65 nm-node CMOS technology for general-purpose system-on-a-chip (SoC), in which both standby and active power reductions are strongly required. With highly reliable triple gate oxide (1.3 nm, 1.6 nm and 3.2 nm) using low damage process, an average standby current can be reduced to one-fifth compared with conventional case. Gate pre-doping(More)
A single chip 2.4 Gb/s optical receiver IC for the next generation access system integrates a preamplifier, automatic offset and gain controller (AGC), phase-locked loop (PLL) and 1:8 demultiplexer (DEMUX) using a 0.15 /spl mu/m bulk CMOS process, realizing low cost and low power consumption. The preamplifier reduces the effect of noise caused by substrate(More)
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm<sup>2</sup> and SRAM cell of 0.124 mum<sup>2</sup> for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is(More)
A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. I<sub>on</sub> of 525/295 muA/mum at I<sub>on</sub> of 20(More)
We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled(More)
A new raised source/drain (RSD) structure is proposed, which combines facet controlled in-situ-doped selective Si epitaxial growth (SEG) and solid-phase diffusion (SPD). This can provide ultra-shallow junctions without sacrificing the parasitic resistance or capacitance. 0.1 /spl mu/m pMOSFETs with 20 nm deep junctions exhibiting excellent electrical(More)
Ultra-low noise characteristics have been obtained in deep-sub-micron Si MOSFETs and Si MMICs by the new low-capacitance interconnect technique using polyimide inter-level dielectrics. The key issue is how to suppress the influence of interconnect parasitics due to the Si substrate. We have achieved 0.13 /spl mu/m Si nMOS with NF/sub min/ of 0.26 dB at 2(More)
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm<sup>2</sup> is realized by breaking down conventional trade-off of leakage power and performance with three key(More)