Learn More
Image scaling plays an important role in digital image processing. It is widely applied in all sorts of display terminals. A new scaling method was proposed in this paper. The method combines traditional nearest neighbor and bilinear methods in a simple but effective way. The hybrid algorithm was discussed based on analysis of its idea origin. Multiple(More)
The hybrid reconfigurable computing system that couples the traditional processor with the reconfigurable hardware is becoming a mainstream today. A new hybrid reconfigurable computing system MPRS (Multi-Pipeline Reconfigurable System) is presented, which has multiple linear arrays for pipelined applications. MPRSpsila architecture and the mapping method(More)
With the development of IC technology and the increasing processing power requirement, more and more processing cores are being integrated into one single chip. One of the key problems is the communication efficiency between the processing cores, and network on chip (NoC) has been proposed as prospect architecture. In this paper, scalability issue of 2-D(More)
With the development of a large scale integrated circuit and semiconductor production process, multi-processor on-chip system provides a feasible solution for the highly parallel computation and communications. In this paper, taking JPEG decoding as the starting point, a decoding system with multi-core processors based on the Avalon bus is presented. The(More)
A new architecture based on parallel FIR systolic arrays for motion compensation interpolation in H.264/AVC is presented in this paper. Unlike other interpolation architectures based on traditional adder tree or one systolic FIR, this design has advantages of both the pipeline property of systolic FIR filter and high parallel property. It has following(More)
A novel architecture FFT processor which can carry on 1-D FFT algorithm or 2-D FFT algorithm corresponding different size of FFT is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for the heterogeneous multi-core SoC on chip application. The mixed architecture FFT processor achieves balance between high processing(More)
An alkaline phosphatase was purified from the gut of sea cucumber Stichopus japonicus by n-butyl alcohol extract, ammonium sulfate precipitation, ion exchange chromatography with diethylaminoethyl cellulose, gel filtration chromatography with Sephacryl S-200 and preparative electrophoresis with polyacrylamide gel electrophoresis. The native enzyme was(More)