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—Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM(More)
Traumatic brain injury (TBI) is a leading cause of sustained impairment in military and civilian populations. However, mild TBI (mTBI) can be difficult to detect using conventional MRI or CT. Injured brain tissues in mTBI patients generate abnormal slow-waves (1-4 Hz) that can be measured and localized by resting-state magnetoencephalography (MEG). In this(More)
In our everyday lives, we perceive emotional information via multiple sensory channels. This is particularly evident for emotional faces and voices in a social context. Over the past years, a multitude of studies have addressed the question of how affective cues conveyed by auditory and visual channels are integrated. Behavioral studies show that hearing(More)
—In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR).(More)
A 4096×2160p multiview video encoder chip is implemented on a 3.95mm×2.90mm die with 90nm CMOS technology. A view-parallel macroblock-interleaved scheduling with 8-stage macroblock pipelined architecture achieves 212Mpix-els/s throughput, which is 3.4× to 7.7× better than the state-of-the-art encoder chips. In addition, 94% on-chip SRAM area and 79%(More)
— The most critical issue of an H.264/AVC decoder is the system architecture design with balanced pipelining schedules and proper degrees of parallelism. In this paper, a hybrid task pipelining scheme is first presented to greatly reduce the internal memory size and bandwidth. Block-level, macroblock-level, and macroblock/frame-level pipelining schedules(More)
The insula has consistently been shown to be involved in processing stimuli that evoke the emotional response of disgust. Recently, its specificity for processing disgust has been challenged and a broader role of the insula in the representation of interoceptive information has been suggested. Studying the temporal dynamics of insula activation during(More)
In this paper, a power-scalable H.264 encoding system is provided with the efforts on both the algorithm and the architecture levels. For a start, a Motion Estimation (ME) pre-skip algorithm is adopted as a system-level power-scalable algorithm. In order to realize a dedicated hardware, a novel reconfigurable Macro-Block (MB) pipelining architecture is(More)
—Because video services become popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus suitable for mobile applications. In this paper, we target at a power-efficient H.264/AVC encoder. The main power consumption in(More)