—A new input matching method making use of shunt–shunt feedback capacitance is introduced. Based on the new input matching method, reconfigurable SiGe low-noise amplifiers (LNAs) by varying shunt–shunt feedback capacitance are proposed. Two approaches are used to vary the shunt–shunt feedback capacitance. One approach is to switch between two different bias… (More)
—The first circuit implementation of quantization noise suppression technique for 16 fractional-frequency synthesizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the… (More)
A quick wireless label-free detection of disease-related C-reactive proteins (CRPs) using a 200-microm-long microelectromechanical systems (MEMS) microcantilever housed in a 7 x 7 mm(2) reaction chamber with a safe reusable feature is reported. The assay time ranges from about 30 min to 3 h, depending on accuracy. The deflection of the microcantilever due… (More)
—A 5.0-GHz-band monolithic direct-conversion receiver front end employing subharmonic mixers (SHMs) is demonstrated in 0.18-m CMOS technology. Instead of using transistors as transconductors, the SHMs adopt on-chip 1:4 transformers to achieve voltage gain, and hence, excellent local-oscillator self-mixing suppression and good linearity can be obtained.… (More)
This paper presents experimental results of an analog baseband circuit with variable bandwidth for WLAN direct conversion receiver in UMC 0.18um CMOS process. A seventh order chebyshev lowpass filter with triple bandwidth is used in the analog baseband circuit. The bandwidth is selectable from 7.56MHz, 19.5MHz, or 26.5MHz. The circuit adopts the servo loop… (More)
—A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-circuit is demonstrated in 0.18-m CMOS technology, where = or .5 in one mode and 2 or 2 +1 in the other mode with = 128–255. When operated in the divide-by-2 2 +1 mode, this circuit outputs a signal with 50% duty… (More)
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