Yu Cao

Publications1,351
h-index81
Citations30,719
Highly Influential Citations1,389
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Predictive Modeling of the NBTI Effect for Reliable Design
This paper presents a predictive model for the negative bias temperature instability (NBTI) of PMOS under both short term and long term operation. Based on the reaction-diffusion (R-D) mechanism,…
View on IEEE
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis
TLDR
This paper develops a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity, and proposes an efficient method to predict the degradation of circuit speed over a long period of time.
View on IEEE
Modeling and minimization of PMOS NBTI effect for robust nanometer design
TLDR
A predictive model is developed for the degradation of NBTI in both static and dynamic operations and key insights are obtained for the development of robust design solutions.
View on ACM
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
TLDR
A new paradigm of predictive MOSFET and interconnect modeling is introduced to specifically address SPICE compatible parameters for future technology generations and comparisons with published data and 2D simulations are used to verify this predictive technology model.
View on IEEE
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology
TLDR
A unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects is presented, and it is demonstrated that the proposed method very well predicts the degradation.
View on IEEE
New generation of predictive technology model for sub-45nm design exploration
  • Wei Zhao, Yu Cao
  • Engineering
    7th International Symposium on Quality Electronic…
  • 27 March 2006
TLDR
A new generation of predictive technology model (PTM) of bulk CMOS for 130nm to 32nm technology nodes is successfully generated and correctly captures process sensitivities in the nanometer regime.
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New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
  • Wei Zhao, Yu Cao
  • Engineering
    IEEE Transactions on Electron Devices
  • 23 October 2006
A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and…
View on IEEE
Recognize Human Activities from Partially Observed Videos
TLDR
A new method that can recognize human activities from partially observed videos in the general case by dividing each activity into multiple ordered temporal segments and applying sparse coding to derive the activity likelihood of the test video sample at each segment is proposed.
View on IEEE
Synaptojanin Is Recruited by Endophilin to Promote Synaptic Vesicle Uncoating
View on Elsevier
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
TLDR
This work systematically explore the trade-offs of hardware cost by searching the design variable configurations, and proposes a specific dataflow of hardware CNN acceleration to minimize the memory access and data movement while maximizing the resource utilization to achieve high performance.
View on ACM
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