Youngchul Cho

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On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip communication network, communication interfaces of processor/IP/memory, on-chip memory, etc.). For an efficient exploration of its design space, we need fast scheduling and timing(More)
In the design of a heterogeneous multiprocessor system on chip, we face a new design problem; scheduler implementation. In this paper, we present an approach to implementing a static scheduler, which controls all the task executions and communication transactions of a system according to a pre-determined schedule. For the scheduler implementation, we(More)
This paper presents a case study on fast prototyping of a wireless CDMA cellular phone system. We set up a fast prototyping flow which aims at reducing the coverification time. We captured executable specifications of the system with Ptolemy and Polis tools. We developed a prototyping board, a board debugger which provides in-circuit emula-tion functions,(More)
To achieve fast verification of the software part of embedded system, we propose to run the target processor optimistically , which effectively reduces the synchronization overhead with other simulators. For the optimistic processor execution, we present a processor execution platform and state saving/restoration methods. We performed optimistic execution(More)
<italic>In estimating the performance of multiple-cache IP-based systems, we face a problem of interdependency between cache configuration and system behavior. In this paper, we investigate the effects of the interdependency on system performance in a case study. We present a method that gives fast and accurate estimation of system performance by simulating(More)
Software synthesis from a data-flow model has been a very promising technique, especially for multimedia applications with contradicting requirements of high design complexity and fast time-to-market. In a dataflow model, buffer size is pessimistically determined through static analysis, thus results in large memory overhead even with optimization(More)
In this paper, we propose an approach that combines emulation and simulation for efficient debugging of system-on-chip design. The approach is based on an existing technique called cut-based debugging. We also adopt simulation result compression technique to alleviate the problem of potential blow-up in the data size of monitored signals. The approach has(More)