YoungGun Pu

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This paper presents a low power CMOS frequency synthesizer for GPS application that can support multiple reference clocks. The frequency synthesizer has fractional-N phase locked loop structure with sigma-delta modulator to allow multiple reference clock frequencies. The measured phase noise is -126dBc/Hz at 1MHz offset from the carrier. This chip is(More)
In this paper, class-E power amplifier (PA) with automatic power control loop and load compensation circuit is presented. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This(More)
This brief presents a wide-locking-range injectionlocked frequency divider (ILFD) that uses an automatic frequency calibration loop. The proposed ILFD uses the ring oscillator to provide the high division ratio with small chip area. A dualinjection scheme is proposed in order to achieve the wide locking range of the ILFD. The free-running frequency of the(More)
08:00 REGISTRATION: Lecture Theatre J, LTJ, HKUST 09:00-09:10 Opening Ceremony 09:10-09:20 Welcome Address: Professor Roland Chin, Vice President for Academic Affairs, HKUST 09:20-09:40 Committees Address: General and Program Chairs 09:40-10:20 Keynote by Professor Niraj K. Jha, EEE Department, Princeton University, USA “Digital System Testing: Emerging(More)