Young-Kwan Park

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This paper presents an exhaustive method to characterize the interconnect capacitances with taking the floating dummy-tills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is(More)
In this paper, the influence of floating dummy metal-fills on interconnect parasitic is analyzed with the variations of possible factors which can affect the capacitance. Recently proposed chip-level metal-fill modeling, replacing metal-fill layer with effective high-k dielectric, has been reviewed in detail. Using a systematized modeling flow, the property(More)
1. Methodology of development for the process layout aware modeling. The predictive model includes some simple physics-based equations to model process variations and layout effects. (a) (b) Figure 2. The major variable parameters of (a) process and (b) layout in this work. Abstract—A predictive MOSFET model is very critical for early circuit design in(More)
– An efficient characterization technique with the spatial correlation matrix from electrical device parameters such as threshold voltage and saturation current accounting for inter-and intra-die variations is demonstrated. Then, a unified statistical model based on the correlation matrix is developed and implemented to the SPICE simulator to predict the(More)
— Device and circuit lifetime is investigated for poly silicon gated MOSFET. New findings are: (1) More than 1 order lifetime is increased by quantifying the influence of poly depletion effect (PDE) and accumulated trap charge effect (ATCE). (2) We demonstrate that conventional lifetime model produce an incorrect and reverse lifetime result for each(More)
One of the major challenges in deep submicron semiconductor era is to control the increase of variations due to decreasing in feature size. Currently, Design for Manufacturing (DFM) method enables to optimize layouts reducing the influence of process variations on circuit [1]. In this paper, we investigated the process margin analysis methods which are(More)
Triple gate FinFET is emerging as a promising candidate for the future CMOS device structures because of its immunity to short-channel effect. However, the suppression of GIDL is a significant challengefor its application. In this paper, we discuss the characteristics of GIDL on FinFET and extensively analyze the influence of the device technology on GIDL.(More)