Young-Kwan Park

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In this paper, the influence of floating dummy metal-fills on interconnect parasitic is analyzed with the variations of possible factors which can affect the capacitance. Recently proposed chip-level metal-fill modeling, replacing metal-fill layer with effective high-k dielectric, has been reviewed in detail. Using a systematized modeling flow, the property(More)
A multilevel level cell (MLC) technique for flash memories reduces the bit cost and enhances the memory density. However, it is difficult to get a required sensing margin for MLC due to the need for the tight threshold voltage control. We present a novel unified statistical model which can account for interand intra-die variations. The proposed model is(More)
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